By utilising Design Compiler Graphical’s congestion optimisations, we eliminated this routing congestion upfront without having to increase our chip area, and taped out successfully ahead of schedule.”ĭesign Compiler Graphical extends DC Ultra™ topographical technology to predict routing congestion “hot spots” early in the design flow, providing designers with visualisation of congested circuit regions and performing specialised synthesis optimisations to minimise congestion in these areas. “As we enhanced the feature set of our next generation DSP, we saw severe routing congestion due to tight chip area requirements. “We strive to deliver innovative hearing-aids to our customers, and minimising the size and power consumption of these devices is critical to our success,” said Mogens Balsby, director of Silicon Engines at Oticon. To alleviate this congestion, Oticon’s RTL designers deployed the congestion optimisations in Design Compiler Graphical during RTL synthesis, resulting in an easy to route netlist and predictable design closure ahead of schedule. This was especially challenging due to the routing congestion caused by the added functionality, which could have led to multiple design iterations and a longer design schedule. Engineers at Oticon, a world leader in the design, development and manufacture of hearing aids, needed to add new features to the next generation DSP without increasing design area and while maintaining a very tight schedule. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Oticon taped out the digital signal processor (DSP) chipset for their next generation hearing-aid devices ahead of schedule using Synopsys’ Design Compiler(tm) Graphical RTL Synthesis, a key component of the Galaxy™ implementation platform.
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